Astera Labs

Semiconductor Manufacturing asteralabs.com

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Browse 5 Astera Labs Cadence jobs for Aug 2026 in Semiconductor Manufacturing paying $185K to $240K/year. Work as a Analog Mixed-Signal Layout Intern, Principal Analog Mixed-Signal Design Engineer, and Principal Digital RTL Engineer.

Open Jobs

Salary Range

$185K – $240K

Astera Labs Cadence Jobs

Azure C++ CI/CD Cadence Design Engineer Ethernet Excel FPGA InfiniBand Linux NVLink PCIe Program Manager Python RDMA Reinforcement Learning SQL Technical Documentation Technical Recruiter

Cities

San Jose 20 Singapore 2 Duisburg 2 Taipei 1 Jiuquan 1 Bengaluru 1

Countries

United States 60 Singapore 4 Germany 4 Taiwan 2 China 2 India 2

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Full Time Internship

Principal Physical Design Engineer

Astera Labs / San Jose, United States / Staff

Python NVLink PCIe

$185K – $230K 12D

Analog Mixed-Signal Layout Intern

Astera Labs / Singapore, Singapore / Entry

PCIe Ethernet Cadence

13D

Senior Principal Engineer PD

Astera Labs / Singapore, Singapore / Staff

NVLink PCIe Ethernet

13D

Principal Digital RTL Engineer

Astera Labs / San Jose, United States / Staff

PCIe Ethernet Cadence

$185K – $240K 14D

Principal Analog Mixed-Signal Design Engineer

Astera Labs / San Jose, United States / Staff

NVLink PCIe Ethernet

$207K – $230K 19D